Copper (Cu) is replacing aluminum as the material of choice for wiring of microelectronic devices, such as microprocessors and memories. However, the presence of copper in semiconductors such as silicon causes defects that can prevent the proper functioning of transistors formed in the semiconductor. Copper also increases the leakage of current through insulators, such as silicon dioxide, placed between the copper wires. Therefore use of copper wiring demands that efficient diffusion barriers surround the copper wires, to keep the copper confined to its proper locations.
While many efforts at providing diffusion barrier layers around copper have been attempted, they all suffer from some form of disadvantage. Disadvantages include unacceptably high dielectric constant (such as SiC or Si3N4) leading to increased capacitances lowering the speed with which signals can be transmitted through the copper wiring, difficulties in processing (such as electroless deposition of CoWP or CoWB) leading to electrical shorts over insulators between copper wires, increased resistance of copper through incorporation of other materials (such as CoWP, CoWB, or Mn) used to form the barrier layers, increased resistance of copper through restriction of the copper grain growth during anneal caused by presence of impurities (such as Mn), poor adhesion of the barrier layer (such as MnOx) to copper, and the like.
Other efforts have focused on growth of the copper layer, such as growth of copper in narrow trenches and holes (also called vias) on top of barrier layers. To this effect, iodine has been proposed as a suitable catalyst in growing copper using a CVD technique. However, because iodine does not readily adhere to the barrier layers (such as TaN and TiN), a thin copper seeding layer or activation of the barrier layer with plasma pretreatment is needed within the trenches and holes, which has been extremely difficult to perform.